The present invention relates to a spread spectrum clock generation circuit which generates a clock signal the period of which changes slightly in order to reduce electromagnetic wave radiation, a jitter generation circuit which adds a jitter to a clock signal or the like, and a semiconductor device using the circuits.
Recently, as semiconductor devices have increased in speed and degree of integration, a problem of EMI (electromagnetic interference) due to electromagnetic wave radiation from a device has attracted more attention. As the operation frequency has increased, the wavelength has become shorter and shorter, and the wiring length of a connecting circuit, or inside the substrate, has become almost as short as the wavelength of a high frequency signal, therefore, the connecting sections of wires or the like may serve as antennas and electromagnetic wave radiation is increased. The electromagnetic wave radiation of electronic devices using semiconductor devices which operate at a high clock frequency causes adverse effects such as malfunctions due to mutual interference between electronic device and interference with communication devices.
In order to solve these problems, measures are currently taken against electronic devices, which cause the problem of the electromagnetic wave radiation, in which the electromagnetic wave radiation is reduced by improving the arrangement or the like of circuits, the leakage of electromagnetic waves is reduced by shielding the electromagnetic waves, and so on. However, as portable equipment or the like is required to be more compact and lighter, a problem occurs in that it is difficult to sufficiently carry out the shielding in order to reduce the electromagnetic wave radiation.
Therefore, often, the operating clock frequency of a semiconductor device is changed slightly and/or the peak of noise is scattered by the addition of a jitter to a clock signal.
In Japanese Unexamined Patent Publication (Kokai) No. 2000-101424, a spread spectrum clock generation (SSCG) circuit has been proposed, which carries out spread spectrum processing for slightly changing the operating clock frequency of a semiconductor device.
FIG. 1 is a diagram showing a configuration example of a conventional SSCG circuit. This example shows a circuit which generates a clock CK from a reference clock CLK, the frequency of the clock CK being M/N times that of the reference clock CLK, by utilizing a PLL (Phase Locked Loop) circuit. This circuit consists of a 1/N divider 11, a frequency phase comparator 12, a charge pump (CP) 13, a loop-filter 14, a voltage control oscillator (VCO) 17, a 1/M divider 18, a modulator 15, and a voltage addition circuit 16. The frequency phase comparator 12 detects a phase difference between the CLK divided by a factor of N and the CK divided by a factor of M and outputs a signal to control the CP 13 in accordance with the phase difference. The CP 13 outputs a signal to charge and discharge the loop-filter 14 in accordance with the phase difference and a differential voltage in accordance with the phase difference is generated at one end of the loop-filter 14. In a conventional clock generation circuit which does not carry out the spread spectrum modulation, the differential voltage is applied to the VCO 17 and a clock with a constant period is generated accordingly. In the SSCG circuit, however, the modulator 15 outputs a spectrum modulation signal which has a small amplitude and changes in a predetermined spread spectrum modulation period as shown in FIG. 2, and the spectrum modulation signal is added to the differential voltage in the voltage addition circuit 16 and applied to the VCO 17. An amplitude of the spectrum modulation signal is sufficiently smaller than that of the differential signal and the spread spectrum modulation period is sufficiently longer than a period of the generated clock CK. As a result, the period of the generated clock CK changes in the a predetermined cycle, with the period M/N times the period of the reference clock CLK being the center. The coefficient of change of period and the cycle are determined by the spectrum modulation signal generated by the modulator. The response time of the PLL circuit is set to a time sufficiently longer than the period of the spectrum modulation signal.
U.S. Pat. No. 5,488,627 and Japanese Unexamined Patent Publication (Kokai) No. 9-98152 have suggested the use of a waveform as shown in FIG. 3 as a spectrum modulation signal. The use of this waveform makes the peak lower and reduces the electromagnetic wave radiation.
Japanese Unexamined Patent Publication (Kokai) No. 8-292820 has disclosed a configuration in which the period of a spectrum modulation signal is changed randomly. The electromagnetic wave radiation is reduced by randomly changing the period.
Japanese Unexamined Patent Publication (Kokai) No. 7-202652 has disclosed a clock pulse generator which adds a jitter to a clock signal. The clock pulse generator disclosed in Japanese Unexamined Patent Publication (Kokai) No. 7-202652 comprises a plurality of delay circuits connected in series and a multiplexer connected via a tap to the output of each delay circuit. The clock signal to be input from each delay circuit via the tap to the multiplexer becomes a signal delayed in phase with respect to the reference phase respectively, and any one of signals delayed in phase is output selectively by controlling the multiplexer.
Moreover, Japanese Unexamined Patent Publication (Kokai) No. 11-110067 has disclosed a semiconductor device in which the period of a clock signal is constant and the peak value of the EMI intensity is reduced by scattering the EMI intensity to each frequency component by changing the duty ratio.